(Here is the J1 paper I presented at EuroForth 2010).
J1 is a small (200 lines of Verilog) stack-based CPU, intended for FPGAs. A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA. Some highlights:

  • Extremely high code density. A complete system including the TCP/IP stack fits in under 8K bytes.
  • Single cycle call, zero cycle return
  • Instruction set maps trivially to Forth
  • Cross compiler runs on Windows, Mac and Unix
  • Basic software includes a sizeable subset of ANS Forth and a portable TCP/IP networking stack.

J1 was originally designed to run the six
WGE100 Ethernet cameras
in the
Willow Garage PR2 robot.
More recently it was shown at
SVFIG Forth Day 2010
an XESS FPGA board (see Loading the XESS XSA-3S1000 from Python) running a few demonstration programs, including
space invaders, Forth source invaders.fs.
The code is at j1demo.tar.gz.
About the J1¶
The J1 is a simple 16-bit CPU. It has some RAM, a program counter
(PC), a data stack and a call/return stack. It has a small set of
built-in arithmetic instructions. Fields in the J1 instructions
control the arithmetic function, and write the results back to the
data stacks. There are more details on instruction coding in the
The J1 is probably close to the simplest possible useful CPU.
Forth on the J1¶
The CPU was designed to run Forth programs very efficiently: the
machine’s instructions are so close to Forth that there is little
benefit to writing code in assembler. Effectively Forth is the
assembly language. J1 runs at about 100 Forth MIPS on a typical
FPGA. This compares with about 0.1 Forth MIPS for a
traditional threaded Forth running on an embedded 8-bit CPU.
To build the j1 binary j1.bin with gforth, do:
$ cd j1demo/firmware
$ make j1.bin
The code that defines the basic Forth operations as J1
instructions is in basewords.fs
The next layer up defines basic operations in terms of these simple
words. These include many of the CORE words from the DPANS94 Forth
standard. Some of the general facilities provided by

  • byte memory access
  • string handling
  • double precision (i.e. 32 bit) math
  • one’s complement addition
  • memory copy and fill
  • multiplication and division, fractional arithmetic
  • pictured numeric output
  • debug words: memory and stack dump, assert

The above files – about 2K of code – bring the J1 to the point where
it can start to define application-specific code.
The TCP/IP Stack¶
Ethernet driver¶
The Ethernet driver is responsible for packet reception and
transmission. This component deals with the various supported
pieces of MAC hardware
Supported hardware for the Ethernet driver:

  • The Microchip ENC28J60
  • The open source MAC used in the PR2’s cameras
  • The AX88796 used in the XESS development board eth-ax88796.fs

Network components¶
Address Resolution Protocol. The ARP module maintains a small
cache of ARP network addresses, and responds to ARP queries for
our Ethernet address. arp.fs
Internet Protocol. The ip module constructs the IP header. ip.fs
User Datagram Protocol packet construction. udp.fs
Optional DHCP client implementation. This allows the network device
to get its IP address automatically.
Optional Network Time Protocol client.
Optional Domain Name System client.
More VHDL, Verilog and FPGA notes.

You may also like